(1) Field of the Invention
The invention relates to digital signal processing and, more particularly, to a method and system to recover a digital signal by sampling at an optimal phase.
(2) Description of the Prior Art
The demand for higher bit rates by the communications industry has led to the development of high speed and low cost serial link technology. Applications, such as computer-to-computer or computer-to-peripheral interconnection, are requiring high bit rates for both short distances and long distances. However, as data rates increase, losses due to cables and parasitics limit the bandwidth of data links. Improvements in data reliability and bit error rate (BER) are needed.
Referring now to FIG. 1, a prior art digital communications system is shown. A first device, NODE 1 10, is coupled to a second device, NODE 2 14, by a transmission line 18. The first device 10 is sending a stream of digital data 22 out the DOUT pin. This data 22 is encoded as a series of high and low levels. The length of time that the signal is high or low determines whether a “0” value or a “1” value has been encoded. These time lengths are encoded using the first node oscillator OSC1 signal as a time reference.
The data signal 22 is received at the second node DIN pin 14. The second node 22 will decode the incoming signal by determining, first, whether the signal is in a high or low state. Then the length of time in the high/low state is measured to decode a “0” or a “1” value. The second node oscillator OSC2 signal is used as a time reference for decoding the received data. The successful reception and decoding of the digital data signal is called data recovery.
Successful reception of the transmitted signal 22 requires that every bit sent is received and decoded to the proper value. If, for example, a bit “0” is received and decoded improperly as a bit “1”, then a bit error has occurred. The number of bit errors occurring over time is called the bit error rate (BER) of the system. Many factors can contribute to the BER of a digital system. A first problem is ambient noise 28 coupling onto the transmission line 18. Ambient noise sources 28, such as electromagnetic interfere (EMI) or wire-to-wire capacitive coupling, can cause momentary distortions in the data signal 22 waveform. These distortions cause the received waveform at the DIN pin to be decoded improperly.
A second problem is synchronization of the time references of the first and second nodes 10 and 14. In the ideal scenario, each node would use a common system clock reference. However, this is not normally possible. Therefore, as in this example, each node typically has an independent, free-running oscillator. Further, each oscillator, OSC1 and OSC2, is based on an independent crystal 24 and 26. Variations in manufacturing and in operating conditions will cause a frequency mismatch in OSC1 and OSC2. In addition, the periodic transitions of the two clocks will not be synchronized. Further, one clock may drift in frequency over time independently of the other clock.
To provide a means of clock synchronization, delay lock loops (DLL) or phase lock loops (PLL) have been applied in general to generate a synchronous base. The synchronous base is a clocking signal that is used to sample and decode the incoming data signal. The DLL or PLL circuits use a feedback scheme to generate a clocking frequency based on the frequency of the incoming data signal. The use of DLL and PLL provide for improved synchronization and frequency matching, but these approaches have limitation. It is found that noise 28 coupled onto the transmission channel 18 strongly reduces the signal-to-noise ratio (SNR) of the data transmitted. The combination of low SNR and non-ideal clocking effects due to the DLL or PLL frequently results in poor BER performance. This poor BER is especially found in applications near the bandwidth limits due to cable losses and parasitic effects.
Several prior art inventions relate to digital transmission, reception, and data recovery methods and devices. U.S. Pat. No. 6,229,859 to Jeong et al discloses a method and system for transmission and recovery of original digital data. The method includes over-sampling and a phase lock loop. U.S. Pat. No. 5,218,677 to Bono et al shows a computer system high speed link. U.S. Pat. No. 6,107,946 to Jeong et al discloses a system for high speed synchronization and data communications.